Typically, the virtual memory management system in a data processor is a function devised to make effective use of the physical memory. When the required memory size for execution of a particular process is less than the available physical memory, it is possible to carry out the process by mapping to the physical memory. However, when the memory size required by the process is larger than the physical memory, the process typically has to be divided so that only selected sub-portions are mapped to the physical memory as needed.
Typically, a system in which the mapping to the physical memory is controlled and carried out as a batch by an OS (Operating System) in such a manner that the process itself is not aware of the mapping to the physical memory is called a virtual memory management system.
In a virtual memory management system, a sufficiently large virtual memory, as compared to the physical memory, is provided to allow the process to be mapped to the virtual memory. Because of this, even when a plurality of processes exist substantially simultaneously, each process operates only on the virtual memory. An MMU (Memory Management Unit), which is ordinarily controlled by the OS, is adopted for the mapping from the virtual memory to the physical memory. The MMU updates the physical memory so that virtual memory necessary for the process is mapped smoothly to the physical memory. The update of the physical memory is carried out between secondary memories. Hereinafter, an address space in the virtual memory will be referred to as virtual address space while an address space in the physical memory will be referred to as physical address space.
Although it is possible to realize the function of the MMU via software only, typically it is not efficient to carry out the translation via software every time the process accesses the physical memory. Accordingly, a translation lookaside buffer (TLB) for performing address translation is provided as part of the hardware to store frequently used address translation information. The TLB can be considered as a cache for the address translation information. When address translation is carried out from the virtual memory to the physical memory using the MMU, if the translation information has not been registered in the TLB, the MMU issues a TLB miss exception and registers new address translation information in the TLB. However, unlike the cache, when the address translation has failed, i.e., when the TLB miss exception is issued, the replacement of the address translation information is ordinarily carried out via software.
It has been determined that problems exist when it is desired to expand the physical memory in a virtual memory management system. As for the virtual memory management system, it was initially assumed that only a relatively small physical address space was desired for the virtual address space from the viewpoint of actual cost and mounting space. However, owing to the tendency of large capacity and low cost of DRAM (Dynamic Random Access Memory) typically used for main memory, it has become possible to allow a physical address space equivalent in size to the typically desired virtual address space. As a result, in certain situations it has become easier to extend the main memory as the physical address space.
FIG. 7 illustrates an example of a conventional approach involving an allocation of a virtual address space to the physical address space. In this example, the virtual address space is defined via 32 bits while the physical address space is defined via 29 bits. The size of the virtual address space depends on the bit length that handles the address. In a 32-bit microprocessor, the virtual address space is an area of 4 G bytes (or “4 GB”), i.e., the 32nd power of 2. On the other hand, the physical address space depends on the size for mounting actual memory and various bus interfaces. For example, in a microprocessor having a physical address space of 29 bits, the physical address space is an area of 512 M bytes (0.5 GB); i.e., the 29th power of 2.
A buffer in which is registered address translation information to carry out address translation from the virtual address space to the physical address space is the TLB. In the example of FIG. 7, a portion included in the area P0 (2 GB) of the virtual address space is subjected to the address translation into the physical address space of 0.5 GB by the TLB. On the other hand, since P1 and P2, which follow P0, are the areas excluded from the TLB translation, a physical address may be generated via a fixed address mapping system, whereby the upper 3 bits of the virtual address is fixed to 0. Due to this, P1 and P2 are assumed respectively to be 0.5 GB, the same as the physical address space.
The reason why P1 and P2 are assumed as the fixed address mapping system is described below. In the example of FIG. 7, it has been described above that the area of P0 is subjected to address translation by the TLB. Herein, it is presumed that a TLB miss has occurred, which indicates the fact that desired address translation information has not been registered in the TLB. In this case, the MMU generates a TLB miss exception, and the OS registers new address translation information in the TLB. The program that performs the TLB replacement is generally stored in a particular area where the virtual address is fixedly mapped in the physical address without being subjected to address translation. As an example, referring to FIG. 7, the program that performs the TLB replacement may be allocated to area P2 of the virtual address. The reason of the above is as described below. If it is adapted so that areas P1 and P2 are also subjected to the address translation by the TLB, when a TLB miss has occurred, there is a possibility that the TLB replacement program for processing the TLB miss cannot be accessed due to a new TLB miss. Thus, in the virtual address system, the particular software of the system may require a virtual address area for mapping a fixed address in the physical address.
In the conventional system of FIG. 7, based on an assumption that the physical address space maximum is 0.5 GB, the mapping of the virtual address space is determined. Since it is possible to perform a fixed address mapping from the space of P1 or P2 to any address in the physical address space of 0.5 GB, there is no limitation on the fixed address mapping. On the other hand, when the physical address space is extended from 0.5 GB in the conventional system, since only the 0.5 GB within the extended physical address space is the area that allows the fixed address mapping, it is necessary to carry out the fixed address mapping by selecting the area in the design of the hardware. However, as will be discussed in more detail below, since the area requiring the fixed address mapping varies depending on the system, it typically is necessary to customize the hardware of each system. As a result, typically it is difficult to flexibly cope with the extension of the physical address. For example, since the fixed mapping area of P1 and P2 is the hardware that sets the upper 3 bits of the virtual address to 0, the fixed mapping area of P1 and P2 is linked to 0.5 GB only at the start of the physical address. Also, although P1 and P2 have a space of 0.5 GB respectively, some applications do not need 0.5 GB for the fixed address mapping area. As will be discussed in more detail below in connection with embodiments of the present invention, if it is possible to use a page subjected to the fixed address mapping, and a page subjected to the address translation, while appropriately separating the pages from each other, it is possible to use the virtual address space more efficiently.
It is an object of the invention to provide systems and methods for a data processor capable of extending the size of, mainly, the physical address space. Another object of the invention is to provide systems and methods for ensuring that a supervisor program performing TLB replacement does not issue misses to the TLB. Furthermore, it is another object of the present invention to provide a feature allowing the users who may not use the MMU to extend the size of the physical address space.